-------- Original-Nachricht -------- Betreff: Formal Methods for GALS Design Datum: Sun, 28 Aug 2005 12:30:55 +0200 Von: EURASIP JES Alert es@alert.hindawi.com An: gustaf.neumann@wu-wien.ac.at
EURASIP Journal on Embedded Systems
Special Issue on
Formal Methods for GALS Design
Call for Papers
As chips grow in speed and complexity, global control of an entire chip using a single clock is becoming increasingly challenging. In the future, multicore and large-scale systems-on-chip (SoC) designs are therefore likely to be composed of several timing domains.
Global Asynchrony and Local Synchrony (GALS) is emerging as the paradigm of choice for SoC design with multiple timing domains. In GALS systems, each timing domain is locally clocked, and asynchronous communication schemes are used to glue all of the domains together. Thus, unlike purely asynchronous design, GALS design is able to make use of the significant industrial investment in synchronous design tools.
There is an urgent need for the development of sound models and formal methods for GALS systems. In synchronous designs, formal methods and design automation have played an enabling role in the continuing quest for chips with ever greater complexity. Due to the inherent subtleties of the asynchronous circuit design, formal methods are likely to be vital to the success of the GALS paradigm.
We invite original articles for a special issue of the journal to be published in 2006. Articles may cover every aspect related to formal modeling and formal methods for GALS systems and/or target any type of embedded applications and/or architectures combining synchronous and asynchronous notions of timing:
o formal design and synthesis techniques for GALS systems o design and architectural transformations and equivalences o formal verification of GALS systems o formal methods for analysis of GALS systems o hardware compilation of GALS system o latency-insensitive synchronous systems o mixed synchronous-asynchronous systems o synchronous/asynchronous interaction at different levels o clocking, interconnect, and interface issues in deep-submicron design o modeling of interfaces between multiple timing domains o system decomposition into GALS systems o formal aspects of system-on-chip (SoC) and network-on-chip (NoC) designs o motivating case studies, comparisons, and applications.
Authors should follow the EURASIP JES' manuscript format described at the journal's web site: http://www.hindawi.com/journals/es/. Prospective authors should submit an electronic copy of their complete manuscript through the EURASIP JES' manuscript tracking system at the journal's web site, according to the following timetable.
Manuscript Due December 15, 2005 Acceptance Notification April 15, 2006 Final Manuscript Due July 15, 2006 Publication Date 4th Quarter, 2006
GUEST EDITORS:
Alain Girault, Pop Art Project, INRIA Rhône-Alpes, 38334 Saint-Ismier Cedex, France; alain.girault@inrialpes.fr
S. Ramesh, Department of Computer Science and Engineering, Indian Institute of Technology, Bombay, Mumbai-400 076, India; ramesh@cse.iitb.ac.in
Sandeep Kumar Shukla, Electrical and Computer Engineering Department, Virginia Tech, Blacksburg, VA 24061, USA; sandeep@cs.albany.edu
Jean-Pierre Talpin, ESPRESSO, IRISA/INRIA Rennes, 35042 Rennes Cedex, France; jean-pierre.talpin@irisa.fr
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