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Call for Participation
Workshop on Hierarchical Parallelism for Exascale Computing
---HiPar20---
Held in conjunction with SC20, Atlanta, GA.
In cooperation with: IEEE and TCHPC.
www.hipar.net
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Summary ================================
High Performance Computing (HPC) platforms are evolving towards
having fewer but more powerful nodes, driven by the increasing
number of physical cores in multiple sockets and accelerators. The
boundary between nodes and networks is starting to blur, with some
nodes now containing tens of compute elements and memory
sub-systems connected via a memory fabric. The immediate
consequence is an increase in complexity due to ever more complex
architectures (e.g., memory hierarchies), novel accelerator
designs, and energy constraints. Spurred largely by this trend,
hierarchical parallelism is gaining momentum. This approach
embraces, rather than avoiding, the intrinsic complexity of
current and future HPC systems by exploiting parallelism at all
levels: compute, memory and network. This workshop focuses on
hierarchical parallelism. It aims to bring together application,
hardware, and software practitioners proposing new strategies to
fully exploit computational hierarchies, and examples to
illustrate their benefits to achieve extreme scale parallelism.
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Scope and Aims ================================
HiPar20 is designed to showcase new studies, approaches, and
cutting-edge ideas on hierarchical parallelism for extreme-scale
computing. We welcome papers and talks from the HPC community
addressing the use of emerging architectures — focusing
particularly on those characterized by fewer but more powerful
nodes as well as systems with hierarchical network with tiered
communication semantics. Specifically, the emphasis is on the
design, implementation, and application of programming models for
multi-level parallelism, including abstractions for hierarchical
memory access, heterogeneity, multi-threading, vectorization, and
energy efficiency, as well as scalability and performance studies
thereof.
Of particular interest are models addressing these concerns
portably: providing ease of programming and maintaining
performance in the presence of varied accelerators, hardware
configurations, and execution models. Studies that explore the
merits of specific approaches to addressing these concerns, such
as generic programming or domain specific languages, are also in
scope. The workshop is not limited to the traditional HPC software
community. As one example, another key topic is the use of
hierarchical parallelism in dealing with the challenges arising in
machine learning due to the growing importance of this field, the
large scale of systems tackled in that area, and the increasing
interest from more traditional HPC areas.
A goal of HiPar20 is to highlight not just success stories but
also discuss drawbacks and challenges. HiPar20 welcomes HPC
practitioners from all areas, ranging from hardware and compiler
experts to algorithms and software developers, to present and
discuss the state of the art in emerging approaches to utilize
multi-level parallelism for extreme scale computing.
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Topics
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Submissions are encouraged in, but not limited to the following
areas:
* Hierarchical work scheduling and execution;
* Hardware, software, and algorithmic advances for efficient use
of memory hierarchies, multi-threading and vectorization;
* Efficient use of nested parallelism, for example CUDA dynamic
parallelism, for large scale simulations;
* Programming heterogeneous nodes;
* Leading-edge programming models, for example fully distributed
task-based models and hybrid MPI+X, with X representing shared
memory parallelism via threads, vectorization, tasking or parallel
loop constructs. * Implementations of algorithms that are natural
fits for nested work (for example approaches that use recursion);
* Challenges and successes in managing computing hierarchies;
* Examples demonstrating effective use of the combination of
inter-node and intra-node parallelism;
* Novel approaches leveraging asynchronous execution to maximize
efficiency;
* Challenges and successes of porting of existing applications to
many-core and heterogeneous platforms;
* Recent developments in compiler optimizations for emerging
architectures;
* Applications of hierarchical programming models from emerging AI
fields, for example deep learning and extreme-scale data
analytics.
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Submission Guidelines ================================
We solicit submissions in the following categories:
(a) Regular research papers: Intended for submissions describing
original work and ideas that have not appeared in another
conference or journal, and are not currently under review for any
other conference or journal. Regular papers must be at least (6)
and must not exceed (10) letter size pages (U.S. letter –
8.5"x11").
Accepted regular papers will be published in the workshop
proceedings in cooperation with IEEE TCHPC.
(b) Short papers: Intended for material that is not mature enough
for a full paper, to present novel, interesting ideas or
preliminary results that will be formally submitted elsewhere.
Short papers must not exceed four (4) pages.
Short papers will NOT be included in the proceedings.
Please note that: - The page limits above only apply to the core
text, content-related appendices, and figures. References and
reproducibility appendix do not count against the page limit.
- When deciding between submissions with comparable evaluations,
priority will be given to those with higher quality of
presentation and whose focus relates more directly to the workshop
themes.
- Papers must be submitted electronically at
https://submissions.supercomputing.org/ and must follow the IEEE
format:
www.ieee.org/conferences/publishing/templates.html
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Reproducibility Initiative
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HiPar20 follows the SC20 reproducibility and transparency
initiative. The SC20 details can be found at:
https://sc20.supercomputing.org/submit/transparency-reproducibility-initiative.
HiPar20 requires all submission to include an Artifact Description
(AD) Appendix. Note that the AD will be auto-generated from author
responses to a form embedded in the online submission system. The
Artifact Evaluation (AE) remains optional.
We also encourage authors to follow the transparency initiative
for two reasons: (a) it helps the authors themselves with the
actual writing and structuring of the paper to express the
research process; (b) it helps readers understand the thinking
process used by the authors to plan, obtain and explain their
results.
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Coronavirus and HiPar20
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We are monitoring the situation on a daily basis, following
closely the SC20 updates:
https://sc20.supercomputing.org/attend/coronavirus-sc/
https://sc20.supercomputing.org/2020/03/10/hpc-supports-pandemic-research-efforts/
We are brainstorming about hosting the workshop in a virtual
setting, should SC20 become digital. Please refer to our HiPar20
website
www.hipar.net for latest updates.
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Important dates ================================
Submission Deadline: August 31, 2020 (AoE)
Author Notification: September 14, 2020
Camera Ready: October 5, 2020
Final Program: October 9, 2020
Workshop Date: Sun Nov 15, 9am-5:30pm
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Chairs and Committees
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Workshop chair: - Francesco Rizzi NexGen Analytics
Organizing Committee: - D.S. Hollman Sandia National Labs
- Lee Howes Facebook
- Xiaoye Sherry Li Lawrence Berkeley National Lab
Program Committee Chairs:
- Christian Trott Sandia National Labs
- Filippo Spiga NVIDIA
Program Committee:
- Mark Bull EPCC
- Carlo Cavazzoni CINECA
- Benjamin Cumming CSCS
- Chris Forster NVIDIA
- Marta Garcia Gasulla BSC
- Anja Gerbes Geothe Uni.Frankfurt
- Mark Hoemmen Stellar Science
- Toshiyuki Imamura RIKEN
- Guido Juckeland Helmholtz Center
- Hartmut Kaiser LSU
- Vivek Kale Brookhaven Labs
- Jonathan Lifflander Sandia National Labs
- James Lin Shanghai J.Tong Univ.
- Aram Markosyan Xilinx - Rui Oliveira INESC TEC
- Philippe Pebay NexGen Analytics
- Zhiqi Tao Intel
- Flavio Vella Univ. of Bozen
- Michèle Weiland EPCC
- Jeremiah Wilke Sandia National Labs
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Contact information:
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For questions, please email us at:
hiparws@gmail.com