-------- Original-Nachricht -------- Betreff: CMOS RF Circuits for Wireless Applications Datum: Fri, 29 Apr 2005 08:09:07 +0200 Von: EURASIP JWCN Alert wcn@hindawi.info An: gustaf.neumann@wu-wien.ac.at
EURASIP Journal on Wireless Communications and Networking
Special Issue on
CMOS RF Circuits for Wireless Applications
Call for Papers
Advanced concepts for wireless communications present a vision of technology that is embedded in our surroundings and practically invisible, but present whenever required. From established radio techniques like GSM, 802.11, or Bluetooth to more emerging ones like ultra-wideband (UWB) or smart dust moats, a common denominator for future progress is underlying CMOS technology. Although the use of deep-submicron CMOS processes allows for an unprecedented degree of scaling in digital circuitry, it complicates implementation and integration of traditional RF circuits. The explosive growth of standard cellular radios and radically different new wireless applications makes it imperative to find architectural and circuit solutions to these design problems.
Two key issues for future silicon-based systems are scale of integration and ultra-low power dissipation. The concept of combining digital, memory, mixed-signal, and RF circuitry on one chip in the form of System-on-Chip (SoC) has been around for a while. However, the difficulty of integrating heterogeneous circuit design styles and processes onto one substrate still remains. Therefore, System-in-Package (SiP) concept seems to be gaining more acceptance.
While it is true that heterogeneous circuits and architectures originally developed for their native technologies cannot be effectively integrated �as is� into a deep-submicron CMOS process, one might ask the question whether those functions can be ported into more CMOS-friendly architectures to reap all the benefits of the digital design and flow. It is not predestined that RF wireless frequency synthesizers be always charge-pump-based PLLs with VCOs, RF transmit upconverters be I/Q modulators, receivers use only Gilbert cell or passive continuous-time mixers. Performance of modern CMOS transistors is nowadays good enough for multi-GHz RF applications.
Low power has always been important for wireless communications. With new developments in wireless sensor networks and wireless systems for medical applications, the power dissipation is becoming a number one issue. Wireless sensor network systems are being applied in critical applications in commerce, healthcare, and security. These systems have unique characteristics and face many implementation challenges. The requirement for long operating life for a wireless sensor node under limited energy supply imposes the most severe design constraints. This calls for innovative design methodologies at the circuit and system level to address this rigorous requirement.
Wireless systems for medical applications hold a number of advantages over wired alternatives, including the ease of use, reduced risk of infection, reduced risk of failure, reduced patient discomfort, enhanced mobility, and lower cost. Typically, applications demand expertise in multiple disciplines, varying from analog sensors to digital processing cores, suggesting opportunities for extensive hardware integration.
The special issue will address the state of the art in CMOS design in the context of wireless communication for 3G/4G cellular telephony, wireless sensor networks, and wireless medical applications.
Topics of interest include (but are not limited to):
o Hardware aspects of wireless networks o Wireless CMOS circuits for healthcare and telemedicine o Modulation schemes for low-power RF transmission o RF transceiver architectures (low IF, direct conversion, super-regenerative) o RF signal processing o Phase-locked loops (PLLs) o Digitally controlled oscillators o LNAs, mixers, charge pumps, and VCOs in CMOS o System-on-Chip (SoC) and System-in-Package (SiP) implementations o RF design implementation challenges in deep-submicron CMOS processes
Authors should follow the EURASIP JWCN manuscript format described at the journal site http://www.hindawi.info/wcn/ Prospective authors should submit an electronic copy of their complete manuscript through the EURASIP JWCN's manuscript tracking system at journal's web site, according to the following timetable.
Manuscript Due September 1, 2005 Acceptance Notification January 1, 2006 Final Manuscript Due April 1, 2006 Publication Date 2nd Quarter, 2006
GUEST EDITORS:
Kris Iniewski, Department of Electrical and Computer Engineering, University of Alberta, ECERF Building, Edmonton, AB, Canada T6G 2V4; iniewski@ece.ualberta.ca
Mourad El-Gamal, Department of Electrical and Computer Engineering, McGill University, McConnell Engineering Building, Room 633, 3480 University Street, Montreal, QC, Canada H3A 2A7; mourad@macs.ece.mcgill.ca
Robert Bogdan Staszewski, Texas Instruments, Dallas, TX75243, USA; b-staszewski@ti.com
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